HAL OSPI constants migration ¶

This section provides information about the HAL OSPI constants migration.

Note

All constants are migrated using the following concept: Replace Finite Parameter Defines (Including PPP Instances) with Enum Types at HAL Levels..

HAL OSPI IO manager IO port ¶

There are only two available ports, HAL_XSPIM_IOPORT_3 to HAL_XSPIM_IOPORT_8 are not physically present. They were removed in HAL2.

For more details refer to: HAL OSPI IO manager configuration type definition.

HAL1	HAL2
#define HAL_OSPIM_IOPORT_NONE #define HAL_OSPIM_IOPORT_1_LOW #define HAL_OSPIM_IOPORT_1_HIGH #define HAL_OSPIM_IOPORT_2_LOW #define HAL_OSPIM_IOPORT_2_HIGH #define HAL_OSPIM_IOPORT_3_LOW #define HAL_OSPIM_IOPORT_3_HIGH #define HAL_OSPIM_IOPORT_4_LOW #define HAL_OSPIM_IOPORT_4_HIGH #define HAL_OSPIM_IOPORT_5_LOW #define HAL_OSPIM_IOPORT_5_HIGH #define HAL_OSPIM_IOPORT_6_LOW #define HAL_OSPIM_IOPORT_6_HIGH #define HAL_OSPIM_IOPORT_7_LOW #define HAL_OSPIM_IOPORT_7_HIGH #define HAL_OSPIM_IOPORT_8_LOW #define HAL_OSPIM_IOPORT_8_HIGH	typedef enum { HAL_XSPI_XSPIM_IO_NONE, HAL_XSPI_XSPIM_XSPI1_IO_LOW, HAL_XSPI_XSPIM_XSPI1_IO_HIGH, HAL_XSPI_XSPIM_XSPI2_IO_LOW, HAL_XSPI_XSPIM_XSPI2_IO_HIGH, HAL_XSPI_XSPIM_XSPI1_XSPI2_IO_LOW, HAL_XSPI_XSPIM_XSPI1_XSPI2_IO_HIGH, } hal_xspi_xspim_io_t;

HAL1

HAL2

                #define HAL_OSPIM_IOPORT_NONE
#define HAL_OSPIM_IOPORT_1_LOW
#define HAL_OSPIM_IOPORT_1_HIGH
#define HAL_OSPIM_IOPORT_2_LOW
#define HAL_OSPIM_IOPORT_2_HIGH



#define HAL_OSPIM_IOPORT_3_LOW
#define HAL_OSPIM_IOPORT_3_HIGH
#define HAL_OSPIM_IOPORT_4_LOW
#define HAL_OSPIM_IOPORT_4_HIGH
#define HAL_OSPIM_IOPORT_5_LOW
#define HAL_OSPIM_IOPORT_5_HIGH
#define HAL_OSPIM_IOPORT_6_LOW
#define HAL_OSPIM_IOPORT_6_HIGH
#define HAL_OSPIM_IOPORT_7_LOW
#define HAL_OSPIM_IOPORT_7_HIGH
#define HAL_OSPIM_IOPORT_8_LOW
#define HAL_OSPIM_IOPORT_8_HIGH

               

                typedef enum
{
  HAL_XSPI_XSPIM_IO_NONE,
  HAL_XSPI_XSPIM_XSPI1_IO_LOW,
  HAL_XSPI_XSPIM_XSPI1_IO_HIGH,
  HAL_XSPI_XSPIM_XSPI2_IO_LOW,
  HAL_XSPI_XSPIM_XSPI2_IO_HIGH,
  HAL_XSPI_XSPIM_XSPI1_XSPI2_IO_LOW,
  HAL_XSPI_XSPIM_XSPI1_XSPI2_IO_HIGH,
} hal_xspi_xspim_io_t;

               

HAL OSPI address size ¶

HAL1	HAL2
#define HAL_OSPI_ADDRESS_8_BITS #define HAL_OSPI_ADDRESS_16_BITS #define HAL_OSPI_ADDRESS_24_BITS #define HAL_OSPI_ADDRESS_32_BITS	typedef enum { HAL_XSPI_ADDR_8BIT, HAL_XSPI_ADDR_16BIT, HAL_XSPI_ADDR_24BIT, HAL_XSPI_ADDR_32BIT, } hal_xspi_addr_width_t;

HAL1

HAL2

                #define HAL_OSPI_ADDRESS_8_BITS
#define HAL_OSPI_ADDRESS_16_BITS
#define HAL_OSPI_ADDRESS_24_BITS
#define HAL_OSPI_ADDRESS_32_BITS

               

                typedef enum
{
  HAL_XSPI_ADDR_8BIT,
  HAL_XSPI_ADDR_16BIT,
  HAL_XSPI_ADDR_24BIT,
  HAL_XSPI_ADDR_32BIT,
} hal_xspi_addr_width_t;

               

HAL OSPI address mode ¶

HAL1	HAL2
#define HAL_OSPI_ADDRESS_NONE #define HAL_OSPI_ADDRESS_1_LINE #define HAL_OSPI_ADDRESS_2_LINES #define HAL_OSPI_ADDRESS_4_LINES #define HAL_OSPI_ADDRESS_8_LINES	typedef enum { HAL_XSPI_ADDR_NONE, HAL_XSPI_ADDR_1LINE, HAL_XSPI_ADDR_2LINES, HAL_XSPI_ADDR_4LINES, HAL_XSPI_ADDR_8LINES } hal_xspi_addr_mode_t;

HAL1

HAL2

                #define HAL_OSPI_ADDRESS_NONE
#define HAL_OSPI_ADDRESS_1_LINE
#define HAL_OSPI_ADDRESS_2_LINES
#define HAL_OSPI_ADDRESS_4_LINES
#define HAL_OSPI_ADDRESS_8_LINES

               

                typedef enum
{
  HAL_XSPI_ADDR_NONE,
  HAL_XSPI_ADDR_1LINE,
  HAL_XSPI_ADDR_2LINES,
  HAL_XSPI_ADDR_4LINES,
  HAL_XSPI_ADDR_8LINES
} hal_xspi_addr_mode_t;

               

HAL OSPI alternate bytes mode ¶

HAL1	HAL2
#define HAL_OSPI_ALTERNATE_BYTES_NONE #define HAL_OSPI_ALTERNATE_BYTES_1_LINE #define HAL_OSPI_ALTERNATE_BYTES_2_LINES #define HAL_OSPI_ALTERNATE_BYTES_4_LINES #define HAL_OSPI_ALTERNATE_BYTES_8_LINES	typedef enum { HAL_XSPI_ALTERNATE_BYTES_NONE, HAL_XSPI_ALTERNATE_BYTES_1LINE, HAL_XSPI_ALTERNATE_BYTES_2LINES, HAL_XSPI_ALTERNATE_BYTES_4LINES, HAL_XSPI_ALTERNATE_BYTES_8LINES } hal_xspi_alternate_bytes_mode_t;

HAL1

HAL2

                #define HAL_OSPI_ALTERNATE_BYTES_NONE
#define HAL_OSPI_ALTERNATE_BYTES_1_LINE
#define HAL_OSPI_ALTERNATE_BYTES_2_LINES
#define HAL_OSPI_ALTERNATE_BYTES_4_LINES
#define HAL_OSPI_ALTERNATE_BYTES_8_LINES

               

                typedef enum
{
  HAL_XSPI_ALTERNATE_BYTES_NONE,
  HAL_XSPI_ALTERNATE_BYTES_1LINE,
  HAL_XSPI_ALTERNATE_BYTES_2LINES,
  HAL_XSPI_ALTERNATE_BYTES_4LINES,
  HAL_XSPI_ALTERNATE_BYTES_8LINES
} hal_xspi_alternate_bytes_mode_t;

               

HAL OSPI alternate bytes size ¶

HAL1	HAL2
#define HAL_OSPI_ALTERNATE_BYTES_8_BITS #define HAL_OSPI_ALTERNATE_BYTES_16_BITS #define HAL_OSPI_ALTERNATE_BYTES_24_BITS #define HAL_OSPI_ALTERNATE_BYTES_32_BITS	typedef enum { HAL_XSPI_ALTERNATE_BYTES_8BIT, HAL_XSPI_ALTERNATE_BYTES_16BIT, HAL_XSPI_ALTERNATE_BYTES_24BIT, HAL_XSPI_ALTERNATE_BYTES_32BIT } hal_xspi_alternate_bytes_width_t;

HAL1

HAL2

                #define HAL_OSPI_ALTERNATE_BYTES_8_BITS
#define HAL_OSPI_ALTERNATE_BYTES_16_BITS
#define HAL_OSPI_ALTERNATE_BYTES_24_BITS
#define HAL_OSPI_ALTERNATE_BYTES_32_BITS

               

                typedef enum
{
  HAL_XSPI_ALTERNATE_BYTES_8BIT,
  HAL_XSPI_ALTERNATE_BYTES_16BIT,
  HAL_XSPI_ALTERNATE_BYTES_24BIT,
  HAL_XSPI_ALTERNATE_BYTES_32BIT
} hal_xspi_alternate_bytes_width_t;

               

HAL OSPI automatic stop ¶

HAL1	HAL2
#define HAL_OSPI_AUTOMATIC_STOP_DISABLE #define HAL_OSPI_AUTOMATIC_STOP_ENABLE	typedef enum { HAL_XSPI_AUTOMATIC_STOP_DISABLED, HAL_XSPI_AUTOMATIC_STOP_ENABLED } hal_xspi_automatic_stop_status_t;

HAL OSPI clock mode ¶

HAL1	HAL2
#define HAL_OSPI_CLOCK_MODE_0 #define HAL_OSPI_CLOCK_MODE_3	typedef enum { HAL_XSPI_CLOCK_LOW, HAL_XSPI_CLOCK_HIGH } hal_xspi_clock_polarity_t;

HAL OSPI data mode ¶

HAL1	HAL2
#define HAL_OSPI_DATA_NONE #define HAL_OSPI_DATA_1_LINE #define HAL_OSPI_DATA_2_LINES #define HAL_OSPI_DATA_4_LINES #define HAL_OSPI_DATA_8_LINES	typedef enum { HAL_XSPI_REGULAR_DATA_NONE, HAL_XSPI_REGULAR_DATA_1LINE, HAL_XSPI_REGULAR_DATA_2LINES, HAL_XSPI_REGULAR_DATA_4LINES, HAL_XSPI_REGULAR_DATA_8LINES, HAL_XSPI_REGULAR_DATA_16LINES } hal_xspi_regular_data_mode_t;

HAL1

HAL2

                #define HAL_OSPI_DATA_NONE
#define HAL_OSPI_DATA_1_LINE
#define HAL_OSPI_DATA_2_LINES
#define HAL_OSPI_DATA_4_LINES
#define HAL_OSPI_DATA_8_LINES

               

                typedef enum
{
  HAL_XSPI_REGULAR_DATA_NONE,
  HAL_XSPI_REGULAR_DATA_1LINE,
  HAL_XSPI_REGULAR_DATA_2LINES,
  HAL_XSPI_REGULAR_DATA_4LINES,
  HAL_XSPI_REGULAR_DATA_8LINES,
  HAL_XSPI_REGULAR_DATA_16LINES
} hal_xspi_regular_data_mode_t;

               

HAL OSPI data DTR mode ¶

HAL1	HAL2
#define HAL_OSPI_DATA_DTR_DISABLE #define HAL_OSPI_DATA_DTR_ENABLE	typedef enum { HAL_XSPI_DATA_DTR_DISABLED, HAL_XSPI_DATA_DTR_ENABLED } hal_xspi_data_dtr_status_t;

HAL OSPI delay block bypass ¶

HAL1	HAL2
#define HAL_OSPI_DELAY_BLOCK_USED #define HAL_OSPI_DELAY_BLOCK_BYPASSED	typedef enum { HAL_XSPI_DLYB_ON, HAL_XSPI_DLYB_BYPASS } hal_xspi_dlyb_state_t;

HAL OSPI delay hold quarter cycle ¶

HAL1	HAL2
#define HAL_OSPI_DHQC_DISABLE #define HAL_OSPI_DHQC_ENABLE	typedef enum { HAL_XSPI_DELAY_HOLD_NONE, HAL_XSPI_DELAY_HOLD_QUARTCYCLE } hal_xspi_delay_hold_t;

HAL OSPI DQS mode ¶

HAL1	HAL2
#define HAL_OSPI_DQS_DISABLE #define HAL_OSPI_DQS_ENABLE	typedef enum { HAL_XSPI_DQS_DISABLED, HAL_XSPI_DQS_ENABLED } hal_xspi_dqs_status_t;

HAL OSPI Dual-Quad ¶

HAL1	HAL2
#define HAL_OSPI_DUALQUAD_DISABLE #define HAL_OSPI_DUALQUAD_ENABLE	typedef enum { HAL_XSPI_MEMORY_SINGLE, HAL_XSPI_MEMORY_DUAL } hal_xspi_memory_mode_t;

HAL OSPI error code ¶

HAL1	HAL2
#define HAL_OSPI_ERROR_NONE #define HAL_OSPI_ERROR_TIMEOUT #define HAL_OSPI_ERROR_TRANSFER #define HAL_OSPI_ERROR_DMA #define HAL_OSPI_ERROR_INVALID_PARAM #define HAL_OSPI_ERROR_INVALID_SEQUENCE #define HAL_OSPI_ERROR_INVALID_CALLBACK	#define HAL_XSPI_ERROR_NONE #define HAL_XSPI_ERROR_TIMEOUT #define HAL_XSPI_ERROR_TRANSFER #define HAL_XSPI_ERROR_DMA Removed; These kinds of logical errors are reported by the direct function return.

HAL1

HAL2

                #define HAL_OSPI_ERROR_NONE
#define HAL_OSPI_ERROR_TIMEOUT
#define HAL_OSPI_ERROR_TRANSFER
#define HAL_OSPI_ERROR_DMA

               

                #define HAL_OSPI_ERROR_INVALID_PARAM
#define HAL_OSPI_ERROR_INVALID_SEQUENCE
#define HAL_OSPI_ERROR_INVALID_CALLBACK

               

                #define HAL_XSPI_ERROR_NONE
#define HAL_XSPI_ERROR_TIMEOUT
#define HAL_XSPI_ERROR_TRANSFER
#define HAL_XSPI_ERROR_DMA

               

Removed; These kinds of logical errors are reported by the direct function return.

HAL OSPI hyperbus latency mode ¶

HAL1	HAL2
#define HAL_OSPI_VARIABLE_LATENCY #define HAL_OSPI_FIXED_LATENCY	typedef enum { HAL_XSPI_LATENCY_VARIABLE, HAL_XSPI_LATENCY_FIXED } hal_xspi_latency_mode_t;

HAL OSPI flags ¶

HAL1	HAL2
#define HAL_OSPI_FLAG_BUSY #define HAL_OSPI_FLAG_TO #define HAL_OSPI_FLAG_SM #define HAL_OSPI_FLAG_FT #define HAL_OSPI_FLAG_TC #define HAL_OSPI_FLAG_TE	#define HAL_XSPI_FLAG_BUSY #define HAL_XSPI_FLAG_TO #define HAL_XSPI_FLAG_SM #define HAL_XSPI_FLAG_FT #define HAL_XSPI_FLAG_TC #define HAL_XSPI_FLAG_TE #define HAL_XSPI_FLAG_ALL

HAL1

HAL2

                #define HAL_OSPI_FLAG_BUSY
#define HAL_OSPI_FLAG_TO
#define HAL_OSPI_FLAG_SM
#define HAL_OSPI_FLAG_FT
#define HAL_OSPI_FLAG_TC
#define HAL_OSPI_FLAG_TE

               

                #define HAL_XSPI_FLAG_BUSY
#define HAL_XSPI_FLAG_TO
#define HAL_XSPI_FLAG_SM
#define HAL_XSPI_FLAG_FT
#define HAL_XSPI_FLAG_TC
#define HAL_XSPI_FLAG_TE
#define HAL_XSPI_FLAG_ALL

               

HAL OSPI flash ID ¶

HAL1	HAL2
#define HAL_OSPI_FLASH_ID_1 #define HAL_OSPI_FLASH_ID_2	typedef enum { HAL_XSPI_IO_7_0, HAL_XSPI_IO_7_4 ... } hal_xspi_io_select_t;

HAL OSPI free running clock ¶

HAL1	HAL2
#define HAL_OSPI_FREERUNCLK_DISABLE #define HAL_OSPI_FREERUNCLK_ENABLE	typedef enum { HAL_XSPI_FREE_RUNNING_CLK_DISABLED, HAL_XSPI_FREE_RUNNING_CLK_ENABLED } hal_xspi_free_running_clk_status_t;

HAL OSPI interrupts ¶

HAL1	HAL2
#define HAL_OSPI_IT_FT #define HAL_OSPI_IT_SM #define HAL_OSPI_IT_TC #define HAL_OSPI_IT_TE #define HAL_OSPI_IT_TO	#define HAL_XSPI_IT_TO #define HAL_XSPI_IT_SM #define HAL_XSPI_IT_FT #define HAL_XSPI_IT_TC #define HAL_XSPI_IT_TE #define HAL_XSPI_IT_ALL

HAL1

HAL2

                #define HAL_OSPI_IT_FT
#define HAL_OSPI_IT_SM
#define HAL_OSPI_IT_TC
#define HAL_OSPI_IT_TE
#define HAL_OSPI_IT_TO

               

                #define HAL_XSPI_IT_TO
#define HAL_XSPI_IT_SM
#define HAL_XSPI_IT_FT
#define HAL_XSPI_IT_TC
#define HAL_XSPI_IT_TE
#define HAL_XSPI_IT_ALL

               

HAL OSPI hyperbus write zero latency activation ¶

HAL1	HAL2
#define HAL_OSPI_LATENCY_ON_WRITE #define HAL_OSPI_NO_LATENCY_ON_WRITE	typedef enum { HAL_XSPI_WRITE_ZERO_LATENCY_ENABLED, HAL_XSPI_WRITE_ZERO_LATENCY_DISABLED } hal_xspi_write_zero_latency_status_t;

HAL OSPI match mode ¶

HAL1	HAL2
#define HAL_OSPI_MATCH_MODE_AND #define HAL_OSPI_MATCH_MODE_OR	typedef enum { HAL_XSPI_MATCH_MODE_AND, HAL_XSPI_MATCH_MODE_OR } hal_xspi_match_mode_t;

HAL OSPI hyperbus address space ¶

HAL1	HAL2
#define HAL_OSPI_MEMORY_ADDRESS_SPACE #define HAL_OSPI_REGISTER_ADDRESS_SPACE	typedef enum { HAL_XSPI_ADDR_MEMORY, HAL_XSPI_ADDR_REGISTER } hal_xspi_addr_space_t;

HAL OSPI memory type ¶

HAL1	HAL2
#define HAL_OSPI_MEMTYPE_MICRON #define HAL_OSPI_MEMTYPE_MACRONIX #define HAL_OSPI_MEMTYPE_APMEMORY #define HAL_OSPI_MEMTYPE_MACRONIX_RAM #define HAL_OSPI_MEMTYPE_HYPERBUS	typedef enum { HAL_XSPI_MEMORY_TYPE_MICRON, HAL_XSPI_MEMORY_TYPE_MACRONIX, HAL_XSPI_MEMORY_TYPE_APMEM, HAL_XSPI_MEMORY_TYPE_MACRONIX_RAM, HAL_XSPI_MEMORY_TYPE_HYPERBUS, HAL_XSPI_MEMORY_TYPE_APMEM_16BIT } hal_xspi_memory_type_t;

HAL1

HAL2

                #define HAL_OSPI_MEMTYPE_MICRON
#define HAL_OSPI_MEMTYPE_MACRONIX
#define HAL_OSPI_MEMTYPE_APMEMORY
#define HAL_OSPI_MEMTYPE_MACRONIX_RAM
#define HAL_OSPI_MEMTYPE_HYPERBUS

               

                typedef enum
{
  HAL_XSPI_MEMORY_TYPE_MICRON,
  HAL_XSPI_MEMORY_TYPE_MACRONIX,
  HAL_XSPI_MEMORY_TYPE_APMEM,
  HAL_XSPI_MEMORY_TYPE_MACRONIX_RAM,
  HAL_XSPI_MEMORY_TYPE_HYPERBUS,
  HAL_XSPI_MEMORY_TYPE_APMEM_16BIT
} hal_xspi_memory_type_t;

               

HAL OSPI operation type ¶

HAL1	HAL2
#define HAL_OSPI_OPTYPE_COMMON_CFG #define HAL_OSPI_OPTYPE_READ_CFG #define HAL_OSPI_OPTYPE_WRITE_CFG #define HAL_OSPI_OPTYPE_WRAP_CFG	typedef enum { HAL_XSPI_OPERATION_COMMON_CFG, HAL_XSPI_OPERATION_READ_CFG, HAL_XSPI_OPERATION_WRITE_CFG, HAL_XSPI_OPERATION_WRAP_CFG } hal_xspi_operation_type_t;

HAL1

HAL2

                #define HAL_OSPI_OPTYPE_COMMON_CFG
#define HAL_OSPI_OPTYPE_READ_CFG
#define HAL_OSPI_OPTYPE_WRITE_CFG
#define HAL_OSPI_OPTYPE_WRAP_CFG

               

                typedef enum
{
  HAL_XSPI_OPERATION_COMMON_CFG,
  HAL_XSPI_OPERATION_READ_CFG,
  HAL_XSPI_OPERATION_WRITE_CFG,
  HAL_XSPI_OPERATION_WRAP_CFG
} hal_xspi_operation_type_t;

               

Hal Ospi register address space constants ¶

HAL1	HAL2
#define HAL_OSPI_MEMORY_ADDRESS_SPACE #define HAL_OSPI_REGISTER_ADDRESS_SPACE	typedef enum { HAL_XSPI_ADDR_MEMORY, HAL_XSPI_ADDR_REGISTER } hal_xspi_addr_space_t;

HAL OSPI sample shifting ¶

HAL1	HAL2
#define HAL_OSPI_SAMPLE_SHIFTING_NONE #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE	typedef enum { HAL_XSPI_SAMPLE_SHIFT_NONE, HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE } hal_xspi_sample_shift_t;

HAL OSPI SIOO mode ¶

HAL1	HAL2
#define HAL_OSPI_SIOO_INST_EVERY_CMD #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD	typedef enum { HAL_XSPI_SIOO_DISABLED, HAL_XSPI_SIOO_ENABLED } hal_xspi_sioo_status_t;

HAL OSPI state ¶

HAL1	HAL2
#define HAL_OSPI_STATE_RESET #define HAL_OSPI_STATE_HYPERBUS_INIT #define HAL_OSPI_STATE_READY #define HAL_OSPI_STATE_BUSY_CMD #define HAL_OSPI_STATE_BUSY_TX #define HAL_OSPI_STATE_BUSY_RX #define HAL_OSPI_STATE_BUSY_AUTO_POLLING #define HAL_OSPI_STATE_BUSY_MEM_MAPPED #define HAL_OSPI_STATE_ABORT #define HAL_OSPI_STATE_ERROR #define HAL_OSPI_STATE_CMD_CFG #define HAL_OSPI_STATE_READ_CMD_CFG #define HAL_OSPI_STATE_WRITE_CMD_CFG	typedef enum { HAL_XSPI_STATE_RESET, HAL_XSPI_STATE_INIT, HAL_XSPI_STATE_IDLE, HAL_XSPI_STATE_CMD_ACTIVE, HAL_XSPI_STATE_TX_ACTIVE, HAL_XSPI_STATE_RX_ACTIVE, HAL_XSPI_STATE_AUTO_POLLING_ACTIVE, HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE, HAL_XSPI_STATE_ABORT, HAL_XSPI_OTFDEC_STATE_ENCRYPT } hal_xspi_state_t;

HAL1

HAL2

                #define HAL_OSPI_STATE_RESET
#define HAL_OSPI_STATE_HYPERBUS_INIT
#define HAL_OSPI_STATE_READY
#define HAL_OSPI_STATE_BUSY_CMD
#define HAL_OSPI_STATE_BUSY_TX
#define HAL_OSPI_STATE_BUSY_RX
#define HAL_OSPI_STATE_BUSY_AUTO_POLLING
#define HAL_OSPI_STATE_BUSY_MEM_MAPPED
#define HAL_OSPI_STATE_ABORT

#define HAL_OSPI_STATE_ERROR
#define HAL_OSPI_STATE_CMD_CFG
#define HAL_OSPI_STATE_READ_CMD_CFG
#define HAL_OSPI_STATE_WRITE_CMD_CFG

               

                typedef enum
{
  HAL_XSPI_STATE_RESET,
  HAL_XSPI_STATE_INIT,
  HAL_XSPI_STATE_IDLE,
  HAL_XSPI_STATE_CMD_ACTIVE,
  HAL_XSPI_STATE_TX_ACTIVE,
  HAL_XSPI_STATE_RX_ACTIVE,
  HAL_XSPI_STATE_AUTO_POLLING_ACTIVE,
  HAL_XSPI_STATE_MEMORY_MAPPED_ACTIVE,
  HAL_XSPI_STATE_ABORT,
  HAL_XSPI_OTFDEC_STATE_ENCRYPT
} hal_xspi_state_t;

               

Related concept: Revised and optimized HAL state machine

HAL OSPI timeout activation ¶

HAL1	HAL2
#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE	typedef enum { HAL_XSPI_TIMEOUT_DISABLE, HAL_XSPI_TIMEOUT_ENABLE } hal_xspi_timeout_activation_t;

HAL OSPI timeout definition ¶

HAL1	HAL2
#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE	Relocated to the source file as a private constant, as it is not intended for direct use by the application.

HAL OSPI wrap-size ¶

HAL1	HAL2
#define HAL_OSPI_WRAP_NOT_SUPPORTED #define HAL_OSPI_WRAP_16_BYTES #define HAL_OSPI_WRAP_32_BYTES #define HAL_OSPI_WRAP_64_BYTES #define HAL_OSPI_WRAP_128_BYTES	typedef enum { HAL_XSPI_WRAP_NOT_SUPPORTED, HAL_XSPI_WRAP_16BYTE, HAL_XSPI_WRAP_32BYTE, HAL_XSPI_WRAP_64BYTE, HAL_XSPI_WRAP_128BYTE } hal_xspi_wrap_size_t;

HAL1

HAL2

                #define HAL_OSPI_WRAP_NOT_SUPPORTED
#define HAL_OSPI_WRAP_16_BYTES
#define HAL_OSPI_WRAP_32_BYTES
#define HAL_OSPI_WRAP_64_BYTES
#define HAL_OSPI_WRAP_128_BYTES

               

                typedef enum
{
  HAL_XSPI_WRAP_NOT_SUPPORTED,
  HAL_XSPI_WRAP_16BYTE,
  HAL_XSPI_WRAP_32BYTE,
  HAL_XSPI_WRAP_64BYTE,
  HAL_XSPI_WRAP_128BYTE
} hal_xspi_wrap_size_t;

               

HAL OSPI alternate bytes DTR mode ¶

HAL1	HAL2
#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE	typedef enum { HAL_XSPI_ALTERNATE_BYTES_DTR_DISABLED, HAL_XSPI_ALTERNATE_BYTES_DTR_ENABLED } hal_xspi_alternate_bytes_dtr_status_t;

HAL1

HAL2

                #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE
#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE

                typedef enum
{
  HAL_XSPI_ALTERNATE_BYTES_DTR_DISABLED,
  HAL_XSPI_ALTERNATE_BYTES_DTR_ENABLED
} hal_xspi_alternate_bytes_dtr_status_t;

               

HAL OSPI instruction size ¶

HAL1	HAL2
#define HAL_OSPI_INSTRUCTION_8_BITS #define HAL_OSPI_INSTRUCTION_16_BITS #define HAL_OSPI_INSTRUCTION_24_BITS #define HAL_OSPI_INSTRUCTION_32_BITS	typedef enum { HAL_XSPI_INSTRUCTION_8BIT, HAL_XSPI_INSTRUCTION_16BIT, HAL_XSPI_INSTRUCTION_24BIT, HAL_XSPI_INSTRUCTION_32BIT } hal_xspi_instruction_width_t;

HAL1

HAL2

                #define HAL_OSPI_INSTRUCTION_8_BITS
#define HAL_OSPI_INSTRUCTION_16_BITS
#define HAL_OSPI_INSTRUCTION_24_BITS
#define HAL_OSPI_INSTRUCTION_32_BITS

               

                typedef enum
{
  HAL_XSPI_INSTRUCTION_8BIT,
  HAL_XSPI_INSTRUCTION_16BIT,
  HAL_XSPI_INSTRUCTION_24BIT,
  HAL_XSPI_INSTRUCTION_32BIT
} hal_xspi_instruction_width_t;

               

HAL OSPI instruction DTR mode ¶

HAL1	HAL2
#define HAL_OSPI_INSTRUCTION_DTR_DISABLE #define HAL_OSPI_INSTRUCTION_DTR_ENABLE	typedef enum { HAL_XSPI_INSTRUCTION_DTR_DISABLED, HAL_XSPI_INSTRUCTION_DTR_ENABLED } hal_xspi_instruction_dtr_status_t;

HAL OSPI address DTR mode ¶

HAL1	HAL2
#define HAL_OSPI_ADDRESS_DTR_DISABLE #define HAL_OSPI_ADDRESS_DTR_ENABLE	typedef enum { HAL_XSPI_ADDR_DTR_DISABLED, HAL_XSPI_ADDR_DTR_ENABLED } hal_xspi_addr_dtr_status_t;

HAL OSPI instruction mode ¶

HAL1	HAL2
#define HAL_OSPI_INSTRUCTION_NONE #define HAL_OSPI_INSTRUCTION_1_LINE #define HAL_OSPI_INSTRUCTION_2_LINES #define HAL_OSPI_INSTRUCTION_4_LINES #define HAL_OSPI_INSTRUCTION_8_LINES	typedef enum { HAL_XSPI_INSTRUCTION_NONE, HAL_XSPI_INSTRUCTION_1LINE, HAL_XSPI_INSTRUCTION_2LINES, HAL_XSPI_INSTRUCTION_4LINES, HAL_XSPI_INSTRUCTION_8LINES } hal_xspi_instruction_mode_t;

HAL1

HAL2

                #define HAL_OSPI_INSTRUCTION_NONE
#define HAL_OSPI_INSTRUCTION_1_LINE
#define HAL_OSPI_INSTRUCTION_2_LINES
#define HAL_OSPI_INSTRUCTION_4_LINES
#define HAL_OSPI_INSTRUCTION_8_LINES

               

                typedef enum
{
  HAL_XSPI_INSTRUCTION_NONE,
  HAL_XSPI_INSTRUCTION_1LINE,
  HAL_XSPI_INSTRUCTION_2LINES,
  HAL_XSPI_INSTRUCTION_4LINES,
  HAL_XSPI_INSTRUCTION_8LINES
} hal_xspi_instruction_mode_t;

               